| Presentation | 1998/7/24 New Three Dimensional (3D) Memory Array Architecture For Future Ultra High Density DRAM Tetsuo Endoh, Katsuhisa Shinmei, Hiroshi Sakuraba, Fujio Masuoka, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Three dimensional(3D)memory array architecture is realized by stacking several cells in series vertically up on each cell which is located in two dimensional(2D)array matrix.Total bit-line capacitance of this proposed architecture's DRAM is suppressed to about 37% of normal DRAM, when one bit-line has 1K-bit cells and the same design rules are used.Moreover, array area of 1M-bit DRAM using the proposed architecture, is reduced to above 11.5% of normal DRAM using the same design rules.By describing above analyses, the advantages of this proposed 3D memory array architecture will be cleared. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | three dimensional(3D)memory / memory array architecture / Stacked-SGT / DRAM / SGT / bit-line capacitance |
| Paper # | SDM98-113,ICD98-112 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 1998/7/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | New Three Dimensional (3D) Memory Array Architecture For Future Ultra High Density DRAM |
| Sub Title (in English) | |
| Keyword(1) | three dimensional(3D)memory |
| Keyword(2) | memory array architecture |
| Keyword(3) | Stacked-SGT |
| Keyword(4) | DRAM |
| Keyword(5) | SGT |
| Keyword(6) | bit-line capacitance |
| 1st Author's Name | Tetsuo Endoh |
| 1st Author's Affiliation | Research Institute of Electrical Communication, Tohoku University,() |
| 2nd Author's Name | Katsuhisa Shinmei |
| 2nd Author's Affiliation | Research Institute of Electrical Communication, Tohoku University, |
| 3rd Author's Name | Hiroshi Sakuraba |
| 3rd Author's Affiliation | Research Institute of Electrical Communication, Tohoku University, |
| 4th Author's Name | Fujio Masuoka |
| 4th Author's Affiliation | Research Institute of Electrical Communication, Tohoku University, |
| Date | 1998/7/24 |
| Paper # | SDM98-113,ICD98-112 |
| Volume (vol) | vol.98 |
| Number (no) | 194 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |