| Presentation | 1998/7/24 A DRAM Module Generator with an Expandable Cell Array Scheme Hideki Takeuchi, Tomoaki Yabe, Shinji Miyano, Takehiko Hojo, Motohiro Enkaku, Masaaki Yamada, Masami Murakata, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes a DRAM Module Generator with an expandable cell array scheme. This approach uses the cell array segment as the unit of increment and applies shared sense amplifier scheme.This approach has enabled us to construct DRAM macros with a wide variety of configurations and reduce layout area of DRAM macros.Using a 0.35μm process technology, a series of DRAM macros with 2112 derivatives has been developed.The macro size using this approach is 17.2% smaller than that of the conventional scheme for a capacity of 32Mbit.The module generator has successfully generated a number of macros, taking five seconds for each macro, including a 32Mbit macro with a 150MHz cycle time. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | embedded / DRAM / macro / ASIC / module generator / metal option |
| Paper # | SDM98-111,ICD98-110 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 1998/7/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A DRAM Module Generator with an Expandable Cell Array Scheme |
| Sub Title (in English) | |
| Keyword(1) | embedded |
| Keyword(2) | DRAM |
| Keyword(3) | macro |
| Keyword(4) | ASIC |
| Keyword(5) | module generator |
| Keyword(6) | metal option |
| 1st Author's Name | Hideki Takeuchi |
| 1st Author's Affiliation | Semiconductor DA & Test Engineering Center, Toshiba Corporation() |
| 2nd Author's Name | Tomoaki Yabe |
| 2nd Author's Affiliation | ULSI Device Engineering Laboratory, Toshiba Corporation |
| 3rd Author's Name | Shinji Miyano |
| 3rd Author's Affiliation | ULSI Device Engineering Laboratory, Toshiba Corporation |
| 4th Author's Name | Takehiko Hojo |
| 4th Author's Affiliation | Semiconductor System Engineering Center, Toshiba Corporation |
| 5th Author's Name | Motohiro Enkaku |
| 5th Author's Affiliation | Semiconductor System Engineering Center, Toshiba Corporation |
| 6th Author's Name | Masaaki Yamada |
| 6th Author's Affiliation | Semiconductor DA & Test Engineering Center, Toshiba Corporation |
| 7th Author's Name | Masami Murakata |
| 7th Author's Affiliation | Semiconductor DA & Test Engineering Center, Toshiba Corporation |
| Date | 1998/7/24 |
| Paper # | SDM98-111,ICD98-110 |
| Volume (vol) | vol.98 |
| Number (no) | 194 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |