| Presentation | 1998/7/24 A Sophisticated Bit-by-Bit Verifying Scheme for NAND EEPROM's Kazushige Kanda, Hiroshi Nakamura, Ken-ichi Imamiya, Koji Sakui, Jun-ichi Miyamoto, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A sophisticated bit-by-bit verifying scheme, which is able to realize the tight programmed threshold voltage distribution of 0.8V, has been proposed for NAND EEPROM's [1].A new bit-by-bit verifying circuit is composed of a conventional sense amplifier and a dynamic latch circuit with only three teansistors, increasing less than 1% chip size of the 64M NAND EEPROM [2]. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | bit-by-bit verifying / threshold voltage distribution / program / NAND EEPROM |
| Paper # | SDM98-110,ICD98-109 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 1998/7/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Sophisticated Bit-by-Bit Verifying Scheme for NAND EEPROM's |
| Sub Title (in English) | |
| Keyword(1) | bit-by-bit verifying |
| Keyword(2) | threshold voltage distribution |
| Keyword(3) | program |
| Keyword(4) | NAND EEPROM |
| 1st Author's Name | Kazushige Kanda |
| 1st Author's Affiliation | ULSI Device Engineering Laboratory, Toshiba Corporation() |
| 2nd Author's Name | Hiroshi Nakamura |
| 2nd Author's Affiliation | ULSI Device Engineering Laboratory, Toshiba Corporation |
| 3rd Author's Name | Ken-ichi Imamiya |
| 3rd Author's Affiliation | ULSI Device Engineering Laboratory, Toshiba Corporation |
| 4th Author's Name | Koji Sakui |
| 4th Author's Affiliation | ULSI Device Engineering Laboratory, Toshiba Corporation |
| 5th Author's Name | Jun-ichi Miyamoto |
| 5th Author's Affiliation | ULSI Device Engineering Laboratory, Toshiba Corporation |
| Date | 1998/7/24 |
| Paper # | SDM98-110,ICD98-109 |
| Volume (vol) | vol.98 |
| Number (no) | 194 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |