| Presentation | 2002/3/1 Closed Expressions for Power Dissipations of CMOS Logic Gates and Their Application to CMOS Circuitries Hiroaki Shikano, Tomochika Harada, Tadayoshi Enomoto, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have developed simple and closed expressions for both a short-circuit power dissipation (Ps) and a charge-discharge power dissipation (po) of a single CMOS logic gate. Ps is expressed by the number (in) of logic gates parallel to a given logic gate and the number (n) of fan-outs of the same gate. Ps and prs expressions for various logic gates including NOT, NAND, NOR, AND-NOR and OR-NAND have been obtained so that the power dissipation of even large circuitries can be easily estimated without using CAD tools, since both m and n are known factors. We applied these expressions to an 8-bit ripple carry adder and an 8-bit square-root, divider circuit. The calculated power dissipations with these expressions were almost the same as these with SPICE. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | CMOS / power dissipation / short-circuit dissipation / ripple carry adder / square-root divider circuit |
| Paper # | ICD2001-242 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2002/3/1(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Closed Expressions for Power Dissipations of CMOS Logic Gates and Their Application to CMOS Circuitries |
| Sub Title (in English) | |
| Keyword(1) | CMOS |
| Keyword(2) | power dissipation |
| Keyword(3) | short-circuit dissipation |
| Keyword(4) | ripple carry adder |
| Keyword(5) | square-root divider circuit |
| 1st Author's Name | Hiroaki Shikano |
| 1st Author's Affiliation | Graduate School of Science and Engineering, Chuo University() |
| 2nd Author's Name | Tomochika Harada |
| 2nd Author's Affiliation | Graduate School of Science and Engineering, Chuo University |
| 3rd Author's Name | Tadayoshi Enomoto |
| 3rd Author's Affiliation | Graduate School of Science and Engineering, Chuo University |
| Date | 2002/3/1 |
| Paper # | ICD2001-242 |
| Volume (vol) | vol.101 |
| Number (no) | 697 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |