Presentation 2001/12/13
ITC coding processor with GA : A proposal of architecture(1)
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Abstract(in English) ITC coding is a system which compresses image date using the redundancy of a picture pattern. ITC coding necds many calculations for searching self-similarity portions. We have introduccd the method which had decreased time for searching of self-similarity portion by GA. However, this algorithm was also difficult for real time processing by general-purpose sequcntial processing computer. We will develop the processor suitable for high-speed execution of ITC coding processor with GA. This processor is based on the VLIW processor. The mcchanism and instruction suitable for high-speed execution is added to this processor
Keyword(in Japanese) (See Japanese page)
Keyword(in English) ITC coding / GA / VLIW
Paper # CPM-120,ICD-172
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Committee ICD
Conference Date 2001/12/13(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) ITC coding processor with GA : A proposal of architecture(1)
Sub Title (in English)
Keyword(1) ITC coding
Keyword(2) GA
Keyword(3) VLIW
1st Author's Name Takeshi FURUKAWA
1st Author's Affiliation Musashi Institute of Technology()
2nd Author's Name Tomo ISHIKAWA
2nd Author's Affiliation Musashi Institute of Technology
3rd Author's Name Arata MIYAUCHI
3rd Author's Affiliation Musashi Institute of Technology
Date 2001/12/13
Paper # CPM-120,ICD-172
Volume (vol) vol.101
Number (no) 518
Page pp.pp.-
#Pages 7
Date of Issue