| Presentation | 2001/8/17 Single Chip Video Processor for Digital HDTV Hideki YAMAUCHI, Kazuhiko TAKETA, Shigeyuki OKADA, Yuh MATSUDA, Tugio MORI, Tsuyoshi WATANABE, Shin'ichiro OKADA, Yoshikazu MIHARA, Naoki TANAHASHI, Yasoo HARADA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have developed a single chip video processor integrated TS decoder, MPEG2 MP@HL decoder and OSD controller for BS digital broadcasting. Adoption of cooperative processing architecture with hardware and software, pipeline architecture and parallel bus architecture allows flexible support of operating frequency reduction, circuit miniaturization, design simplification, high-performance service of BS digital TV, digital TV broadcasting regulation change and equipment specification change. This single chip video processor is manufactured of 0.25-μm four-layer metal CMOS process and the chip size is 10.2 mm^*10.2 mm. The power consumption is 4.5 W when the supply voltage is 2.5 V and operating frequency is 121.5 MHz. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | MPEG2 / SOC / digital TV / Image Compression / Multimedia |
| Paper # | ICD2001-76 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2001/8/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Single Chip Video Processor for Digital HDTV |
| Sub Title (in English) | |
| Keyword(1) | MPEG2 |
| Keyword(2) | SOC |
| Keyword(3) | digital TV |
| Keyword(4) | Image Compression |
| Keyword(5) | Multimedia |
| 1st Author's Name | Hideki YAMAUCHI |
| 1st Author's Affiliation | Microelectronics Research Center, SANYO Electric Co., Ltd.() |
| 2nd Author's Name | Kazuhiko TAKETA |
| 2nd Author's Affiliation | Microelectronics Research Center, SANYO Electric Co., Ltd. |
| 3rd Author's Name | Shigeyuki OKADA |
| 3rd Author's Affiliation | Microelectronics Research Center, SANYO Electric Co., Ltd. |
| 4th Author's Name | Yuh MATSUDA |
| 4th Author's Affiliation | Microelectronics Research Center, SANYO Electric Co., Ltd. |
| 5th Author's Name | Tugio MORI |
| 5th Author's Affiliation | Microelectronics Research Center, SANYO Electric Co., Ltd. |
| 6th Author's Name | Tsuyoshi WATANABE |
| 6th Author's Affiliation | Microelectronics Research Center, SANYO Electric Co., Ltd. |
| 7th Author's Name | Shin'ichiro OKADA |
| 7th Author's Affiliation | Microelectronics Research Center, SANYO Electric Co., Ltd. |
| 8th Author's Name | Yoshikazu MIHARA |
| 8th Author's Affiliation | Hypermedia Research Center, SANYO Electric Co., Ltd. |
| 9th Author's Name | Naoki TANAHASHI |
| 9th Author's Affiliation | Semiconductor Company, SANYO Electric Co., Ltd. |
| 10th Author's Name | Yasoo HARADA |
| 10th Author's Affiliation | Microelectronics Research Center, SANYO Electric Co., Ltd. |
| Date | 2001/8/17 |
| Paper # | ICD2001-76 |
| Volume (vol) | vol.101 |
| Number (no) | 266 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |