| Presentation | 2001/8/17 An LSI Design of the Concurrent Deadlock Recovery Router Recover-x MASATOSHI MIYOTA, TSUTOMU YOSHINAGA, TAKASHl YOKOTA, KANEMITSU OOTSU, TAKANOBU BABA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Interconnection network is an inevitable component in parallel computers. Network router, especially, is a key element for communication ability, that leads system-level performance. Adaptive routing, which can dynamiclly re-route the message, improves performance considerably. It, although, causes deadlocks. We have proposed a new routing method called "Recover-x, " which can detect deadlock state and recover by itself. Our preliminary evaluation shows that the method requires less hardware and performs in a high frequency. In this paper, we report LSI implementation of a Recover-x router. The whole circuits are described in Verilog-HDL. the chip was fabricated using a 1.2μm CMOS technology. The chip size is 7.3mm square and about 12.6K gates are on the chip. The maximum operating frequency is 52.7MHz in our estimation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | parallel computer / interconnection network / router / deadlock / LSI / Verilog-HDL |
| Paper # | ICD2001-69 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2001/8/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An LSI Design of the Concurrent Deadlock Recovery Router Recover-x |
| Sub Title (in English) | |
| Keyword(1) | parallel computer |
| Keyword(2) | interconnection network |
| Keyword(3) | router |
| Keyword(4) | deadlock |
| Keyword(5) | LSI |
| Keyword(6) | Verilog-HDL |
| 1st Author's Name | MASATOSHI MIYOTA |
| 1st Author's Affiliation | Faculty of Engineering, Utsunomiya University() |
| 2nd Author's Name | TSUTOMU YOSHINAGA |
| 2nd Author's Affiliation | Graduate School of Information systems, The University of Electro-Communications |
| 3rd Author's Name | TAKASHl YOKOTA |
| 3rd Author's Affiliation | Faculty of Engineering, Utsunomiya University |
| 4th Author's Name | KANEMITSU OOTSU |
| 4th Author's Affiliation | Faculty of Engineering, Utsunomiya University |
| 5th Author's Name | TAKANOBU BABA |
| 5th Author's Affiliation | Faculty of Engineering, Utsunomiya University |
| Date | 2001/8/17 |
| Paper # | ICD2001-69 |
| Volume (vol) | vol.101 |
| Number (no) | 266 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |