| Presentation | 2001/8/17 A CMOS PLL Clock Generator Using A Back-Gate-Bias Voltage-Controlled Oscillator(BG-VCO) Tomochika Harada, Tadayoshi Enomoto, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A back-gate-bias voltage-controlled oscillator(BG-VCO), whose oscillating frequency ƒ is controlled by a back-gate bias voltage, has been developed. A phase-locked-loop(PLL)clock generator incorporating the BG-VCO was fabricated by using 0.5-μm CMOS technology. The number of MOSFETs in the BG-VCO is less than 1/2 that in a conventional VCO. The voltage sensitivity of a fabricated 41-stage BG-VCO with a single 2.5-V power supply(V_D)is approximately 6.1 MHz/V. Its tuning range and pull-in time are respectively 84.6 MHz to 99.25 MHz and 3.1 μsec. And its peak-to-peak jitter at ƒ_o of 90 MHz and V_D of 2.5 V is less than 252 psec(2.26%). |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | BG-VCO / PLL / back-gate bias / body-bias effect / voltage sensitivity |
| Paper # | ICD2001-66 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2001/8/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A CMOS PLL Clock Generator Using A Back-Gate-Bias Voltage-Controlled Oscillator(BG-VCO) |
| Sub Title (in English) | |
| Keyword(1) | BG-VCO |
| Keyword(2) | PLL |
| Keyword(3) | back-gate bias |
| Keyword(4) | body-bias effect |
| Keyword(5) | voltage sensitivity |
| 1st Author's Name | Tomochika Harada |
| 1st Author's Affiliation | Department of Information and System Engineering Faculty of Science and Engineering Chuo University.() |
| 2nd Author's Name | Tadayoshi Enomoto |
| 2nd Author's Affiliation | Department of Information and System Engineering Faculty of Science and Engineering Chuo University. |
| Date | 2001/8/17 |
| Paper # | ICD2001-66 |
| Volume (vol) | vol.101 |
| Number (no) | 266 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |