Presentation 2001/8/17
Coupling-driven bus design for low-power application-specific systems
Daisuke Yamada, Youngsoo Shin, Hiroshi Kawaguchi, Takayasu Sakurai,
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Abstract(in English) In modern embedded systems including communication and multimedia applications, large fraction of power is consumed during memory access. Thus, buses should be designed and optimized to consume reasonable power while delivering sufficient performance. In this paper, we address a bus ordering problem for low-power application-specific systems. A heuristic algorithm is proposed to determine the order in a way that effective lateral component of capacitance is reduced, thereby reducing the power consumed by buses. Experimental results for various examples indicate that the average power saving from 30% to 46.7% depending on capacitance components can be obtained without any circuit overhead.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Low-power / application-specific system / heuristic algorithm / Bus shuffling
Paper # ICD2001-65
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Conference Date 2001/8/17(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Coupling-driven bus design for low-power application-specific systems
Sub Title (in English)
Keyword(1) Low-power
Keyword(2) application-specific system
Keyword(3) heuristic algorithm
Keyword(4) Bus shuffling
1st Author's Name Daisuke Yamada
1st Author's Affiliation Center for Collaborative Research, University of Tokyo()
2nd Author's Name Youngsoo Shin
2nd Author's Affiliation Center for Collaborative Research, University of Tokyo
3rd Author's Name Hiroshi Kawaguchi
3rd Author's Affiliation Center for Collaborative Research, University of Tokyo
4th Author's Name Takayasu Sakurai
4th Author's Affiliation Center for Collaborative Research, University of Tokyo
Date 2001/8/17
Paper # ICD2001-65
Volume (vol) vol.101
Number (no) 266
Page pp.pp.-
#Pages 8
Date of Issue