| Presentation | 2002/9/23 Realistic Scaling Scenario for Sub-100nm Embedded SRAM Based on 3-Dimensional Interconnect Simulation Yasumasa TSUKAMOTO, Tatsuya KUNIKIYO, Koji NII, Hiroshi MAKINO, Shuhei IWADE, Kiyoshi ISHIKAWA, Yasuo INOUE, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | It is still an open problem to elucidate the scaling merit of the embedded SRAM with the Low Operating Power (LOP) MOSFET's fabrication in 50, 70 and 100nm CMOS technology node. Taking into account the realistic SRAM cell layout, we evaluate the parasitic capacitance of Bit Line (BL) as well as Word Line (WL) in each generation. By means of 3-Dimensional (3D) interconnect simulator (Raphael), we focus on the scaling merit through the comparison of the simulated SRAM BL delay in each CMOS technology node. In this paper, we propose two kinds of original interconnect structure which add some modification to ITRS (International Technology Roadmap for Semiconductors), and clarify for the first time that the original interconnect structures guarantee the scaling merit of the SRAM cell fabricated with the LOP MOSFET's in 50,70 CMOS technology node. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Embedded SRAM / Scaling Merit / 3-dimensional interconnect simulation / 50 and 70nm Technology node |
| Paper # | VLD2002-63 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2002/9/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Realistic Scaling Scenario for Sub-100nm Embedded SRAM Based on 3-Dimensional Interconnect Simulation |
| Sub Title (in English) | |
| Keyword(1) | Embedded SRAM |
| Keyword(2) | Scaling Merit |
| Keyword(3) | 3-dimensional interconnect simulation |
| Keyword(4) | 50 and 70nm Technology node |
| 1st Author's Name | Yasumasa TSUKAMOTO |
| 1st Author's Affiliation | System LSI Development Center() |
| 2nd Author's Name | Tatsuya KUNIKIYO |
| 2nd Author's Affiliation | ULSI Development Center |
| 3rd Author's Name | Koji NII |
| 3rd Author's Affiliation | System LSI Development Center |
| 4th Author's Name | Hiroshi MAKINO |
| 4th Author's Affiliation | System LSI Development Center |
| 5th Author's Name | Shuhei IWADE |
| 5th Author's Affiliation | System LSI Development Center |
| 6th Author's Name | Kiyoshi ISHIKAWA |
| 6th Author's Affiliation | ULSI Development Center |
| 7th Author's Name | Yasuo INOUE |
| 7th Author's Affiliation | ULSI Development Center |
| Date | 2002/9/23 |
| Paper # | VLD2002-63 |
| Volume (vol) | vol.102 |
| Number (no) | 344 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |