| Presentation | 2001/11/22 A Hardware/Software Cosynthesis System for Processors based on Reducing Opration Word Length with Memory Interface Specification Kazuhiro SHIMASHITA, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Let us consider to reduce an area of a processor by shortening the operation word length from n to n/2. In this case, we generally need to excute an operation instruction at least two times in order to obtain n-bit result. However, assume that internal variables in an application program uses only n/2 bits. In this case, we need to execute the operation instruction only once. We have proposed a hardware/software cosynthesis system for processors. In the system, we assume that data length of applications program equals to operation word length of a processor core. This paper proposes an algorithm for shortening an operation word length. The algorithm repeatedly replaces each n bit operation instruction with one or more n/2 bit operation instructions depending on internal variable precision. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | hardware/software cosynthesis / hardware/software partitioning / word length / RISC processor / assembly code |
| Paper # | VLD2001-110,ICD2001-155,FTS2001-57 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2001/11/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Hardware/Software Cosynthesis System for Processors based on Reducing Opration Word Length with Memory Interface Specification |
| Sub Title (in English) | |
| Keyword(1) | hardware/software cosynthesis |
| Keyword(2) | hardware/software partitioning |
| Keyword(3) | word length |
| Keyword(4) | RISC processor |
| Keyword(5) | assembly code |
| 1st Author's Name | Kazuhiro SHIMASHITA |
| 1st Author's Affiliation | Dept.of Electoronics, Information and Communication Engieneering, Waseda University() |
| 2nd Author's Name | Nozomu TOGAWA |
| 2nd Author's Affiliation | Department of Information and Media Sciences, The University of Kitakyushu:Advanced Research Institute for Science and Engineering, Waseda University |
| 3rd Author's Name | Masao YANAGISAWA |
| 3rd Author's Affiliation | Dept.of Electoronics, Information and Communication Engieneering, Waseda University |
| 4th Author's Name | Tatsuo OHTSUKI |
| 4th Author's Affiliation | Dept.of Electoronics, Information and Communication Engieneering, Waseda University |
| Date | 2001/11/22 |
| Paper # | VLD2001-110,ICD2001-155,FTS2001-57 |
| Volume (vol) | vol.101 |
| Number (no) | 467 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |