| Presentation | 2001/11/22 The Processor IP for Research with Software Development Environment Yosuke MITANl, Hiroshi UCHIDA, Tetsuo HIRONAKA, Mattausch HANS JUERGEN, Tetsushi KOIDE, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We developed processor IP which is indispensable for the purpose of shortening period and increasing efficiency in SoC design. Our processor IP for research has the following features. (1) Adopted instruction set which can be used by theexisting software dovelpment evvironment. (2) Architectural design suited for the minimum cireuit area (non-pipelining and internal memory was designed for a single port) (3) According to the purpose reconstruction of IP is freely possible. Moreover, our IP was arranged by some technology. The scale of hardware, clock frequency and a scale of gate are shown as a result. Consequently, we have found that the area of our IP enough to small to be used for a research. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | IP / SuperH / System on Chip / Softmacro / Hardmacro |
| Paper # | VLD2001-109,ICD2001-154,FTS2001-56 |
| Date of Issue |
| Conference Information | |
| Committee | VLD |
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| Conference Date | 2001/11/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | The Processor IP for Research with Software Development Environment |
| Sub Title (in English) | |
| Keyword(1) | IP |
| Keyword(2) | SuperH |
| Keyword(3) | System on Chip |
| Keyword(4) | Softmacro |
| Keyword(5) | Hardmacro |
| 1st Author's Name | Yosuke MITANl |
| 1st Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University() |
| 2nd Author's Name | Hiroshi UCHIDA |
| 2nd Author's Affiliation | Research Center for Nanodevices and Systems, Hroshima University |
| 3rd Author's Name | Tetsuo HIRONAKA |
| 3rd Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| 4th Author's Name | Mattausch HANS JUERGEN |
| 4th Author's Affiliation | Research Center for Nanodevices and Systems, Hroshima University |
| 5th Author's Name | Tetsushi KOIDE |
| 5th Author's Affiliation | Research Center for Nanodevices and Systems, Hroshima University |
| Date | 2001/11/22 |
| Paper # | VLD2001-109,ICD2001-154,FTS2001-56 |
| Volume (vol) | vol.101 |
| Number (no) | 467 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |