Presentation 2001/11/22
A Scheduling Method in High-Level Synthesis for Partial Scan Based on Acyclic Structure
Tomokazu MIURA, Tomoo INOUE, Akio TAMURA, Hideo FUJIWARA,
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Abstract(in English) Acyclic partial scan design is an efficient DFT method. This paper presents a scheduling method in high-level synthesis for reducing the number of scan registers for acyclic structure. In order to estimate the number of scan registers during scheduling, we propose provisional binding, and show a force-directed scheduling algorithm with the provisional binding. Experimental Results show that our scheduling method can reduce the number of scan registers in the resulting RTL datapaths.
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Keyword(in English) acyclic partial scan / high-level synthesis for testability / provisional binding / scheduling
Paper # VLD2001-107,ICD2001-152,FTS2001-54
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Committee VLD
Conference Date 2001/11/22(1days)
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Paper Information
Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Scheduling Method in High-Level Synthesis for Partial Scan Based on Acyclic Structure
Sub Title (in English)
Keyword(1) acyclic partial scan
Keyword(2) high-level synthesis for testability
Keyword(3) provisional binding
Keyword(4) scheduling
1st Author's Name Tomokazu MIURA
1st Author's Affiliation Graduate School of Information Sciences, Hiroshima City University()
2nd Author's Name Tomoo INOUE
2nd Author's Affiliation Faculty of Information Sciences, Hiroshima City University
3rd Author's Name Akio TAMURA
3rd Author's Affiliation Faculty of Information Sciences, Hiroshima City University
4th Author's Name Hideo FUJIWARA
4th Author's Affiliation Graduate School of Information Science, Nara Institute of Sciences and Technology
Date 2001/11/22
Paper # VLD2001-107,ICD2001-152,FTS2001-54
Volume (vol) vol.101
Number (no) 467
Page pp.pp.-
#Pages 6
Date of Issue