| Presentation | 2001/11/22 An algorithm to enumerate all floorplans by using Q-sequence and its applications to the boundary constraint problam Liyan JIN, Keishi SAKANUSHl, Atsushi TAKAHASHl, Hiroshi MURATA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we propose an algorithm to enumerate all floorplans by using Q-sequence Which is an excellent floorplan data structure. For an application, we deal with boundary constraints such that a specified room is abutted on the specified boundary of the chip. We enumerate floorplans satisfying the constraints by the branch and bound method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Floorplan / Q-sequence / Enumeration / Boundary Constraint / Branch and Bound Method |
| Paper # | VLD2001-102,ICD2001-147,FTS2001-49 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2001/11/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An algorithm to enumerate all floorplans by using Q-sequence and its applications to the boundary constraint problam |
| Sub Title (in English) | |
| Keyword(1) | Floorplan |
| Keyword(2) | Q-sequence |
| Keyword(3) | Enumeration |
| Keyword(4) | Boundary Constraint |
| Keyword(5) | Branch and Bound Method |
| 1st Author's Name | Liyan JIN |
| 1st Author's Affiliation | Department of Communications and Integrated Systems, Tokyo Institute of Technology() |
| 2nd Author's Name | Keishi SAKANUSHl |
| 2nd Author's Affiliation | Department of Communications and Integrated Systems, Tokyo Institute of Technology |
| 3rd Author's Name | Atsushi TAKAHASHl |
| 3rd Author's Affiliation | Department of Communications and Integrated Systems, Tokyo Institute of Technology |
| 4th Author's Name | Hiroshi MURATA |
| 4th Author's Affiliation | MicroArk Co., Ltd. |
| Date | 2001/11/22 |
| Paper # | VLD2001-102,ICD2001-147,FTS2001-49 |
| Volume (vol) | vol.101 |
| Number (no) | 467 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |