| Presentation | 2001/11/22 Design and Evaluation of Circuits for Computing Reciprocal Square Root Daisuke MATSUOKA, Naofumi TAKAGl, Kazuyoshi TAKAGl, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Designs and evalaution of reciprocal square root computing circuits based on our previously proposed digit-recurrence algorithm are presented. The input and output of each circuit are in the IEEE-754 floating point basic format. Two different implementation approachs are presented. One following the IEEE-754 rounding and the other allowing an error within 1 ulp (unit in the last place). The designs of radix-2, radix-4, and overlapped radix-2 (radix-4) circuits are presented. For any radix, the area of the circuit that follows the IEEE-754 rounding is about 1.7 times as large as that of the circuit that allows an error within 1 ulp. As a result, we show that the delay of radix-4 circuits is similar to that of the overlapped radix-2 (radix-4) circuits, and that the area of the former become smaller than that of the latter. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | reciprocal square root / hardware algorithm / digit-recurrence algorithm / VLSI |
| Paper # | VLD2001-90,ICD2001-135,FTS2001-37 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2001/11/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design and Evaluation of Circuits for Computing Reciprocal Square Root |
| Sub Title (in English) | |
| Keyword(1) | reciprocal square root |
| Keyword(2) | hardware algorithm |
| Keyword(3) | digit-recurrence algorithm |
| Keyword(4) | VLSI |
| 1st Author's Name | Daisuke MATSUOKA |
| 1st Author's Affiliation | Department of Computational Science and Engineering, Nagoya University() |
| 2nd Author's Name | Naofumi TAKAGl |
| 2nd Author's Affiliation | Department of Information Engineering, Nagoya Univcrsity |
| 3rd Author's Name | Kazuyoshi TAKAGl |
| 3rd Author's Affiliation | Department of Information Engineering, Nagoya Univcrsity |
| Date | 2001/11/22 |
| Paper # | VLD2001-90,ICD2001-135,FTS2001-37 |
| Volume (vol) | vol.101 |
| Number (no) | 467 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |