Presentation | 2001/6/22 VLSI Implementation or High Performance Burst Mode for 128-bit Block Ciphers Yukio MITSUYAMA, Zaldy ANDALES, Takao ONOYE, Isao SHIRAKAWA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | A new cipher mode, called the burst mode, is dedicated to the high performance implementation of Advanced Encryption Standard (AES) and other next generation 128-bit block cipher algorithms. In comparison with the conventional modes, this burst mode achieves a considerable increase in the throughput by employing a noveI stream cipher mechanism, which can encrypt 64 plaintext blocks through 16 times of block cipher encryptions. This paper devises sophisticated software and hardware implementations of this new mode. Experimental results show that the software implementation of the burst mode attains two times a shigh speed as that of the colventional mode, while the hardware implementation of the burst mode with the use of a hardware accelerator, where AES is still performed by software, raises the speed of the software implementation by four times, achieving the maximum rate of 1.3 Gbps. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Cipher Mode / Block Cipher / Stream Cipher / AES / Fast Encryption |
Paper # | CAS2001-41,VLD2001-58,DSP2001-60 |
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Conference Information | |
Committee | VLD |
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Conference Date | 2001/6/22(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | VLSI Design Technologies (VLD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | VLSI Implementation or High Performance Burst Mode for 128-bit Block Ciphers |
Sub Title (in English) | |
Keyword(1) | Cipher Mode |
Keyword(2) | Block Cipher |
Keyword(3) | Stream Cipher |
Keyword(4) | AES |
Keyword(5) | Fast Encryption |
1st Author's Name | Yukio MITSUYAMA |
1st Author's Affiliation | Department of Information Systems Engineering, Graduate School of Engineering, Osaka University() |
2nd Author's Name | Zaldy ANDALES |
2nd Author's Affiliation | Department of Information Systems Engineering, Graduate School of Engineering, Osaka University |
3rd Author's Name | Takao ONOYE |
3rd Author's Affiliation | Department of Communications & Computer Eng., Graduate School of Informatics, Kyoto University |
4th Author's Name | Isao SHIRAKAWA |
4th Author's Affiliation | Department of Information Systems Engineering, Graduate School of Engineering, Osaka University |
Date | 2001/6/22 |
Paper # | CAS2001-41,VLD2001-58,DSP2001-60 |
Volume (vol) | vol.101 |
Number (no) | 144 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |