Presentation 2001/6/22
IEEE1394 Hardware/Software Co-simulation environment and design of its Link layer controller
Hirofumi Yamamoto, Keishi Chikamura, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura,
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Abstract(in English) Co-simulation environment between Verilog-HDL description and software functional model has been constructed, which is dedicated to IEEE1394 serial bus network. Using this environment, IEEE1394 link layer controller is successfully designed. Co-simulation between Verilog-HDL description of the link layer and C++ behavioral description of the physical layer is carried out to verify the functionalities of the designed controller. FPGA implementation result of the link layer controller is also shown.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) IEEE1394 / HW/SW Co-simulation / C/C++ / Verilog-HDL / PHI
Paper # CAS2001-40,VLD2001-57,DSP2001-59
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Conference Information
Committee VLD
Conference Date 2001/6/22(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) IEEE1394 Hardware/Software Co-simulation environment and design of its Link layer controller
Sub Title (in English)
Keyword(1) IEEE1394
Keyword(2) HW/SW Co-simulation
Keyword(3) C/C++
Keyword(4) Verilog-HDL
Keyword(5) PHI
1st Author's Name Hirofumi Yamamoto
1st Author's Affiliation Department of Communications and Computer Engineering, Graduate School of Infomatics, Kyoto University()
2nd Author's Name Keishi Chikamura
2nd Author's Affiliation Department of Communications and Computer Engineering, Graduate School of Infomatics, Kyoto University
3rd Author's Name Tomonori Izumi
3rd Author's Affiliation Department of Communications and Computer Engineering, Graduate School of Infomatics, Kyoto University
4th Author's Name Takao Onoye
4th Author's Affiliation Department of Communications and Computer Engineering, Graduate School of Infomatics, Kyoto University
5th Author's Name Yukihiro Nakamura
5th Author's Affiliation Department of Communications and Computer Engineering, Graduate School of Infomatics, Kyoto University
Date 2001/6/22
Paper # CAS2001-40,VLD2001-57,DSP2001-59
Volume (vol) vol.101
Number (no) 144
Page pp.pp.-
#Pages 8
Date of Issue