Presentation 2001/6/21
Multi-PD method PLL frequency synthesizer by dead-zone method
Yasuaki SUMI, Takao TSUKUTANI, Shigeki OBOTE, Yutaka FUKUI,
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Abstract(in English) In the Phase Locked Loop (PLL) frequency synthesizer, which is uscd in a higher frequency region, the prescaler method is employed in order to adiust the operating frequency of the programmable divider. However, the reference frequency is decreased and the performance of the PLL frequency synthesizer is degraded. Multifold method is one of the counter measures answering the request. In this paper we propose the automatic stop operation method of multi-PD introduced by using positively the dead zone of the phasw detector, in order to reduce the power of multi-PD.
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Keyword(in English) PLL frequency synthesizer / dead zone of phase detector / multi-PD method
Paper # CAS2001-16,VLD2001-33,DSP2001-35
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Committee VLD
Conference Date 2001/6/21(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) Multi-PD method PLL frequency synthesizer by dead-zone method
Sub Title (in English)
Keyword(1) PLL frequency synthesizer
Keyword(2) dead zone of phase detector
Keyword(3) multi-PD method
1st Author's Name Yasuaki SUMI
1st Author's Affiliation Tottori University of Environmental Studies()
2nd Author's Name Takao TSUKUTANI
2nd Author's Affiliation Matsue National College of Technology
3rd Author's Name Shigeki OBOTE
3rd Author's Affiliation Faculty of Engineering, Ibaraki University
4th Author's Name Yutaka FUKUI
4th Author's Affiliation Faculty of Engineering, Tottori University
Date 2001/6/21
Paper # CAS2001-16,VLD2001-33,DSP2001-35
Volume (vol) vol.101
Number (no) 143
Page pp.pp.-
#Pages 7
Date of Issue