| Presentation | 2001/5/11 An Implementation of a switch chip for compiler's static data transfer scheduling T. Morimura, K. Tanaka, K. Iwai, H. Amano, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We proposed a multistage interconnection network R-Clos II for the multiprocessor system ASCA to schedule the data transfer statically. R-Clos II is a multistage network which consists of hierarchically clustering multiple Clos networks with extra intermediate stages. To schedule communications between processors easily, it is also important that a switch architecture supports the compiler's data transfer scheduling. Therefore we propose a new switch architecture, called MGF switch architecture, which has two sets of the transfer channel with a crossbar for scheduled packet and non-scheduled packet respectively. In this paper, the chip feature which we implemented are described and we evaluate it's transfer ability by Verilog-HDL simulation. Additionally, the average latency of MGF switch with 40% larger size hardware are about 40% better than that of single channel normal switch at the most. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | MIN, / Clos Network / multiprocessor / static scheduling / switch architecture |
| Paper # | VLD2001-14 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2001/5/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Implementation of a switch chip for compiler's static data transfer scheduling |
| Sub Title (in English) | |
| Keyword(1) | MIN, |
| Keyword(2) | Clos Network |
| Keyword(3) | multiprocessor |
| Keyword(4) | static scheduling |
| Keyword(5) | switch architecture |
| 1st Author's Name | T. Morimura |
| 1st Author's Affiliation | Keio University() |
| 2nd Author's Name | K. Tanaka |
| 2nd Author's Affiliation | Keio University |
| 3rd Author's Name | K. Iwai |
| 3rd Author's Affiliation | National Defence Academy |
| 4th Author's Name | H. Amano |
| 4th Author's Affiliation | Keio University |
| Date | 2001/5/11 |
| Paper # | VLD2001-14 |
| Volume (vol) | vol.101 |
| Number (no) | 46 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |