| Presentation | 2001/5/11 Evaluation of a PBSF Multistage Interconnection Network with SNAIL-2 D. Shiraishi, T. Hoshino, T. Midorikawa, Y. Kanamori, H. Amano, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | For interconnection in middle scale multiprocessors, PBSF(Piled Banyan Switching Fabrics) was proposed. In order to enhance the bandwidth, it consists of 3-dimentionally connected Omega networks, and the first prototype chip was implemented using VDEC process. A multiprocessor system called SNAIL-2 is developed for evaluating the performance of the PBSF network. Now, a prototype with 4 processors and 4 memory modules is available, while the full scale system consists of 16 processors and 16 memory modules. The PBSF network performance of SNAIL-2 is evaluated with some programs front the benchmark application suit "SPLASH-2", and most programs can be executed 3.5 times faster than those with a single processor. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | multiprocessor / MIN / interconnection network / cache |
| Paper # | VLD2001-13 |
| Date of Issue |
| Conference Information | |
| Committee | VLD |
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| Conference Date | 2001/5/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of a PBSF Multistage Interconnection Network with SNAIL-2 |
| Sub Title (in English) | |
| Keyword(1) | multiprocessor |
| Keyword(2) | MIN |
| Keyword(3) | interconnection network |
| Keyword(4) | cache |
| 1st Author's Name | D. Shiraishi |
| 1st Author's Affiliation | Dept. of Information and Computer Science, Keio University() |
| 2nd Author's Name | T. Hoshino |
| 2nd Author's Affiliation | Dept. of Information and Computer Science, Keio University |
| 3rd Author's Name | T. Midorikawa |
| 3rd Author's Affiliation | Dept. of Information and Computer Science, Keio University |
| 4th Author's Name | Y. Kanamori |
| 4th Author's Affiliation | Dept. of Information and Computer Science, Keio University |
| 5th Author's Name | H. Amano |
| 5th Author's Affiliation | Dept. of Information and Computer Science, Keio University |
| Date | 2001/5/11 |
| Paper # | VLD2001-13 |
| Volume (vol) | vol.101 |
| Number (no) | 46 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |