| Presentation | 2001/5/11 An Implementation of Software Cache System for the multiprocessor system ASCA T. Abe, M. Koibuchi, R. Ogawa, K. Iwai, H. Amano, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | we proposed the multiprocessor system ASCA tailored for the multi-grain parallel processing. In near-fine grain parallel processing, small but frequent date movements with syncronization sre required and the overhead of the communication is the critical point. Furthermore, in some cases the communication overhead decreases the performance worse than the sequential processing on single processor. On the other hand, since the compiler's strict static analysis is available in this grain which does not involve runtime decisions, the overhead of communication can be degraded. However, in practice, an uncertain factor, hit or miss-hit of cache, spoils the precise effective static analisys. To cope with this problem, we proposed a software controlled cache system to eliminate it. The key component of this system is the data transfer controller, called DTC which manages the data transfer instead of the processor, and improve the cache hit rate and access speed, and in better case DTC eliminate syncronizations between Processing Elements. We implemented this DTC and evaluate the software cache system. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Software Cache System / multiprocessor / static scheduling / Data Transfer Controller |
| Paper # | VLD2001-12 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2001/5/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Implementation of Software Cache System for the multiprocessor system ASCA |
| Sub Title (in English) | |
| Keyword(1) | Software Cache System |
| Keyword(2) | multiprocessor |
| Keyword(3) | static scheduling |
| Keyword(4) | Data Transfer Controller |
| 1st Author's Name | T. Abe |
| 1st Author's Affiliation | Keio University() |
| 2nd Author's Name | M. Koibuchi |
| 2nd Author's Affiliation | Keio University |
| 3rd Author's Name | R. Ogawa |
| 3rd Author's Affiliation | Keio University |
| 4th Author's Name | K. Iwai |
| 4th Author's Affiliation | National Defence Academy |
| 5th Author's Name | H. Amano |
| 5th Author's Affiliation | Keio University |
| Date | 2001/5/11 |
| Paper # | VLD2001-12 |
| Volume (vol) | vol.101 |
| Number (no) | 46 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |