| Presentation | 2001/5/11 Trial manufacture of asynchronous switch K. Ishikawa, D. Kawakami, Y. Shibata, H. Amano, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Fully asynchronous 4 inputs/outputs switch is designed on a 0.6μm full-custom CMOS chip, and the performance is evaluated with a circuit level simulator. Using novel arbitration circuits, the chip achieves 1.6Gbits/sec peak throughout and 352Mbits/sec average throughput per one port. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | asynchronous circuit / switch / arbiter / bundle data / method |
| Paper # | VLD2001-10 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2001/5/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Trial manufacture of asynchronous switch |
| Sub Title (in English) | |
| Keyword(1) | asynchronous circuit |
| Keyword(2) | switch |
| Keyword(3) | arbiter |
| Keyword(4) | bundle data |
| Keyword(5) | method |
| 1st Author's Name | K. Ishikawa |
| 1st Author's Affiliation | Dept. of Information and Computer Science, Keio University() |
| 2nd Author's Name | D. Kawakami |
| 2nd Author's Affiliation | Dept. of Information and Computer Science, Keio University |
| 3rd Author's Name | Y. Shibata |
| 3rd Author's Affiliation | Dept. of technology, Nagasaki University |
| 4th Author's Name | H. Amano |
| 4th Author's Affiliation | Dept. of Information and Computer Science, Keio University |
| Date | 2001/5/11 |
| Paper # | VLD2001-10 |
| Volume (vol) | vol.101 |
| Number (no) | 46 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |