| Presentation | 2001/5/11 CAD System for Asynchronous VLSI Ciruit. Yoshiyuki MIYAZAWA, Yuka NAKAGOSHI, Masashi IMAI, Rafael MORIZAWA, Metehah OZCAN, Hiroshi NAKAMURA, Takashi NANYA, Wataru TAKAHASHI, Kazutoshi WAKABAYASHI, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes an entire CAD flow from PTL to layout for asynchronous VLSI circuits, which consists of existing synchronous CAD tools and newly developed asynchronous tools. Though conventional asynchronous design methodology has been based on the request-acknowledge handshaking model, this model is not familiar to synchronous circuits designers. Therefore, we proposed a new asynchronous circuit model which consists of a FSM controller and a datapath including seven control modules such as fork, select, merge, and registers, which is similar to synchronous circuit model and easily acceptable by synchronous circuit designers. The RTL description based on the model is translated into asynchronous circuits based on two-rail two phase model by the proposed CAD system, which adds request-acknowledge signals to function modules and translates the conventional single-rail function modules into two-rail ones and then into fine grain pipelined ones. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Asynchrnous Circuit / VLSI / Logic Synthesis |
| Paper # | VLD2001-9 |
| Date of Issue |
| Conference Information | |
| Committee | VLD |
|---|---|
| Conference Date | 2001/5/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | CAD System for Asynchronous VLSI Ciruit. |
| Sub Title (in English) | |
| Keyword(1) | Asynchrnous Circuit |
| Keyword(2) | VLSI |
| Keyword(3) | Logic Synthesis |
| 1st Author's Name | Yoshiyuki MIYAZAWA |
| 1st Author's Affiliation | NEC Informatec Systems,Ltd.() |
| 2nd Author's Name | Yuka NAKAGOSHI |
| 2nd Author's Affiliation | NEC Informatec Systems,Ltd. |
| 3rd Author's Name | Masashi IMAI |
| 3rd Author's Affiliation | Reserch Center for Advanced Science and Technology, Tokyo University. |
| 4th Author's Name | Rafael MORIZAWA |
| 4th Author's Affiliation | Reserch Center for Advanced Science and Technology, Tokyo University. |
| 5th Author's Name | Metehah OZCAN |
| 5th Author's Affiliation | Reserch Center for Advanced Science and Technology, Tokyo University. |
| 6th Author's Name | Hiroshi NAKAMURA |
| 6th Author's Affiliation | Reserch Center for Advanced Science and Technology, Tokyo University. |
| 7th Author's Name | Takashi NANYA |
| 7th Author's Affiliation | Reserch Center for Advanced Science and Technology, Tokyo University. |
| 8th Author's Name | Wataru TAKAHASHI |
| 8th Author's Affiliation | Reserch CentMulti Media Resach Lab, NEC Corporation. |
| 9th Author's Name | Kazutoshi WAKABAYASHI |
| 9th Author's Affiliation | Multi Media Resach Lab, NEC Corporation. |
| Date | 2001/5/11 |
| Paper # | VLD2001-9 |
| Volume (vol) | vol.101 |
| Number (no) | 46 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |