| Presentation | 2001/3/2 Clock Scheduling Method to Reduce the Peak Power for Semi-synchronous Circuits Tsutomu Utagawa, Atsushi Takahashi, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In synchronous circuits, clock needs to be distributed to all registers simultaneously, and many circuit elements consume the power immediately after the clock arrival time. so the instantaneous power consumption in the whole circuit is maximized at that time. On the other hand. in semi-synchronous circuits, clock dose not need to be distributed to all registers simultaneously, so the peak power is expected to be reduced. The purpose of this work is to make sure that the peak power of semi-synchronous circuits is lower than that of synchronous circuits. The power of whole circuit in each time slot is estimated by considering switching probability each of circuit element. And we propose a method of clock scheduling to reduce the peak power under the constraint that the circuit can work in the minimum clock period. In experiments. the validity of our approach is confirmed. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | semi-synchronous circuit / peak power / switching / low power |
| Paper # | VLD2000-143,ICD2000-219 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2001/3/2(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Clock Scheduling Method to Reduce the Peak Power for Semi-synchronous Circuits |
| Sub Title (in English) | |
| Keyword(1) | semi-synchronous circuit |
| Keyword(2) | peak power |
| Keyword(3) | switching |
| Keyword(4) | low power |
| 1st Author's Name | Tsutomu Utagawa |
| 1st Author's Affiliation | Dept. of Communications and Integrated Systems, Graduate School of Science and Engineering, Tokyo Inst. of Tech.() |
| 2nd Author's Name | Atsushi Takahashi |
| 2nd Author's Affiliation | Dept. of Communications and Integrated Systems, Graduate School of Science and Engineering, Tokyo Inst. of Tech. |
| Date | 2001/3/2 |
| Paper # | VLD2000-143,ICD2000-219 |
| Volume (vol) | vol.100 |
| Number (no) | 646 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |