Presentation 2001/1/5
Design Optimization Method Using Digit Serial Operation for DSP Systems
Yoshiharu WATANABE, Yoshinori TAKEUCHI, Akira KITAJIMA, Masaharu IMAI,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) This paper studies DSP system architecture optimization method using digit serial operation under the throughput constraint. The proposed method can make the DSP system design considering the trade-offs between the hardware cost and the throughtput which are introduced by efficient digit size conversions. Experimental results show the trade-offs between the hardware cost and the throughput and the optimum architecture of DSP system can be decided using proposal digit size conversion algorithm under the throuhput constraint.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Digit Serial Operation / Digita Signal Processing / Hardware Cost Minimization / Digit Size Conversion
Paper # VLD2000-126,CPSY2000-81
Date of Issue

Conference Information
Committee VLD
Conference Date 2001/1/5(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design Optimization Method Using Digit Serial Operation for DSP Systems
Sub Title (in English)
Keyword(1) Digit Serial Operation
Keyword(2) Digita Signal Processing
Keyword(3) Hardware Cost Minimization
Keyword(4) Digit Size Conversion
1st Author's Name Yoshiharu WATANABE
1st Author's Affiliation Department of Informatics and Mathematical Science Graduate School of Engineering Science, Osaka University()
2nd Author's Name Yoshinori TAKEUCHI
2nd Author's Affiliation Department of Informatics and Mathematical Science Graduate School of Engineering Science, Osaka University
3rd Author's Name Akira KITAJIMA
3rd Author's Affiliation Department of Informatics and Mathematical Science Graduate School of Engineering Science, Osaka University
4th Author's Name Masaharu IMAI
4th Author's Affiliation Department of Informatics and Mathematical Science Graduate School of Engineering Science, Osaka University
Date 2001/1/5
Paper # VLD2000-126,CPSY2000-81
Volume (vol) vol.100
Number (no) 532
Page pp.pp.-
#Pages 8
Date of Issue