Presentation 2001/1/5
An Implementation of Parallel Distributed Device Model Evaluation on Circuit Simulation
Tsuyoshi SUZUKI, Hiroyuki YAGI, Ryo DANG,
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Abstract(in English) We propose a parallel distributed device model evaluation algorithm in the circuit simulation. Parallel distributed device model evaluation can speed up while maintaining accuracy, because the approach chosen to speed up SPICE is parallelizetion of device model evaluation. In this paper, we estimate the performance of this circuit simulator using the parallel distributed device model evaluation algorithm. The parallel distributed device model evaluation is able to reduce the device model evaluation to 53.5~68.15% in comparison with the original SPICE2. As a result, our circuit simulator can run 1.7 times faster than the original SPICE2 in the maximum speedup.
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Keyword(in English) circuit simulation / device model evaluation / cluster computing / multithread
Paper # VLD2000-124,CPSY2000-79
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Committee VLD
Conference Date 2001/1/5(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An Implementation of Parallel Distributed Device Model Evaluation on Circuit Simulation
Sub Title (in English)
Keyword(1) circuit simulation
Keyword(2) device model evaluation
Keyword(3) cluster computing
Keyword(4) multithread
1st Author's Name Tsuyoshi SUZUKI
1st Author's Affiliation Hosei University()
2nd Author's Name Hiroyuki YAGI
2nd Author's Affiliation Hosei University
3rd Author's Name Ryo DANG
3rd Author's Affiliation Hosei University
Date 2001/1/5
Paper # VLD2000-124,CPSY2000-79
Volume (vol) vol.100
Number (no) 532
Page pp.pp.-
#Pages 7
Date of Issue