Presentation 2001/1/5
A Hierarchical Parallel and Distributed Placer on a PC Cluster by using Voyager
Norihisa WATANUKI, Yoichi SHIRAISHI,
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Abstract(in English) A hierarchical parallel and distributed placer based on the randomized algorithm is developed. The target of this process is the cell placement problem in the layout design for a logic VLSI chip. This process is implemented by using Java and the core of the parallel and distributed process is realized by using Voyager. In this report, the simulation on one EWS first reveals the acceleration of the cell placement process itself. Then, the actual hierarchical parallel and distributed placement is implemented on a PC cluster by using Voyager and its feasibility is checked. The acceleration itself can not yet be evaluated but the communication overhead is evaluated against some benchmark data and the problems occurred in the communication overhead is revealed.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) VLSI / layout / placement problem / randomized algorithm / parallel and distributed process / Voyager / Java
Paper # VLD2000-123,CPSY2000-78
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Conference Information
Committee VLD
Conference Date 2001/1/5(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Hierarchical Parallel and Distributed Placer on a PC Cluster by using Voyager
Sub Title (in English)
Keyword(1) VLSI
Keyword(2) layout
Keyword(3) placement problem
Keyword(4) randomized algorithm
Keyword(5) parallel and distributed process
Keyword(6) Voyager
Keyword(7) Java
1st Author's Name Norihisa WATANUKI
1st Author's Affiliation Department of Computer Science, Faculty of Engineering, Gunma University()
2nd Author's Name Yoichi SHIRAISHI
2nd Author's Affiliation Department of Computer Science, Faculty of Engineering, Gunma University
Date 2001/1/5
Paper # VLD2000-123,CPSY2000-78
Volume (vol) vol.100
Number (no) 532
Page pp.pp.-
#Pages 8
Date of Issue