| Presentation | 2001/1/5 Semi-Synchronous Clock Tree Construction Under Synchronous Circuit Design Environment Seiichiro ISHIJIMA, Atsushi TAKAHASHI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A ciurcuit in which clock is not necessary distributed to all registers simultaneously, called a semi-synchronous circuit, leads to higher frequency or smaller clock tree of the circuit compared with a synchronous circuit. In this paper, we propose a design method to realize a clock tree of semi-synchronous circuit. The method constructs the clock tree making use of conventional design environment. First, it determines the outlineof the clock tree structure by using the information of gate delay and determines the detail after the placement of the circuit. Next, it determines the clock schedule by using the information of delay including routing delay and realizes the semi-synchronous circuit by inserting buffers into the clock tree. We apply the proposed method to a micro processor design and find that it is easy to apply and that a faster circuit is obtained. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | semi-synchronous circuit / design method / processor / clock tree |
| Paper # | VLD2000-120,CPSY2000-75 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2001/1/5(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Semi-Synchronous Clock Tree Construction Under Synchronous Circuit Design Environment |
| Sub Title (in English) | |
| Keyword(1) | semi-synchronous circuit |
| Keyword(2) | design method |
| Keyword(3) | processor |
| Keyword(4) | clock tree |
| 1st Author's Name | Seiichiro ISHIJIMA |
| 1st Author's Affiliation | Dept. of Communications and Integrated Systems, Graduate School of Science and Engineering, Tokyo Inst.of Tech.() |
| 2nd Author's Name | Atsushi TAKAHASHI |
| 2nd Author's Affiliation | Dept. of Communications and Integrated Systems, Graduate School of Science and Engineering, Tokyo Inst.of Tech. |
| Date | 2001/1/5 |
| Paper # | VLD2000-120,CPSY2000-75 |
| Volume (vol) | vol.100 |
| Number (no) | 532 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |