Presentation 2001/1/5
Dynmaic Reconfigurable Network Node
Takahiro MUROOKA, Toshiaki MIYAZAKI,
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Abstract(in English) We developed a dynamically reconfigurable network node that is tuned for high-speed and complex multlayer packet manipulation. The key idea is a dynamic function assignment mechanism; each packet processing task is assigned to several processing modules in an on-the-fly manner. With this mechanism, we can freely arrange the modules and add extra ones if more processing power is needed. In addition, the processing modules are realized using field programmable gate arrays(FPGAs), content addressable memory(CAM)and micro processing units(MPUs). Thus, the functionality of each module can be dynamically changed at anytime. In this paper, the system concept and its implementation are described with an example application.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Telecommunication node / Dynamic reconfiguration / FPGA / CAM
Paper # VLD2000-118,CPSY2000-73
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Conference Information
Committee VLD
Conference Date 2001/1/5(1days)
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Paper Information
Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Dynmaic Reconfigurable Network Node
Sub Title (in English)
Keyword(1) Telecommunication node
Keyword(2) Dynamic reconfiguration
Keyword(3) FPGA
Keyword(4) CAM
1st Author's Name Takahiro MUROOKA
1st Author's Affiliation NTT Network Innovation Laboratories()
2nd Author's Name Toshiaki MIYAZAKI
2nd Author's Affiliation NTT Network Innovation Laboratories
Date 2001/1/5
Paper # VLD2000-118,CPSY2000-73
Volume (vol) vol.100
Number (no) 532
Page pp.pp.-
#Pages 7
Date of Issue