Presentation	2001/1/5 A Discrete Cosine Transform Circuit with Dynamically Reconfigurable Digit-Serial Computation Kazuhito ITO,
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Abstract(in English)	In the era of deep submicron technology, wire delay on an LSI chip is becoming relatively larger than operation delay. Data communication time by wire delay between processing units could be reduced and hence fast processing can be achieved if nearby processing units are dynamically reconfigured into desired operation type and execute operations on the reconfigured units. Based on the simplicity of reconfiguring digit-serial computation. we propose a compact and fast 1-D discrete cosine transfer circuit with dynamically reconfigurable digit-serial computation. An LSI chip is designed and its speed is measured by a circuit simulator. Results show the effectiveness of the proposed circuit.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	dynamic reconfiguration / digit-serial / DCT / scheduling / VLSI architecture
Paper #	VLD2000-117,CPSY2000-72
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Conference Information
Committee	VLD
Conference Date	2001/1/5(1days)
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Paper Information
Registration To	VLSI Design Technologies (VLD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	A Discrete Cosine Transform Circuit with Dynamically Reconfigurable Digit-Serial Computation
Sub Title (in English)
Keyword(1)	dynamic reconfiguration
Keyword(2)	digit-serial
Keyword(3)	DCT
Keyword(4)	scheduling
Keyword(5)	VLSI architecture
1st Author's Name	Kazuhito ITO
1st Author's Affiliation	Department of Electrical and Electronic Systems, Saitama University()
Date	2001/1/5
Paper #	VLD2000-117,CPSY2000-72
Volume (vol)	vol.100
Number (no)	532
Page	pp.pp.-
#Pages	8
Date of Issue