| Presentation | 2001/1/4 A Scheduling Algorithm for a Dynamic Reconfigurable System Based on Multiple FPGAs Takashi ISHITOBI, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, there has been proposed a dynamically reconfigurable system where a part of the system can be reconfigured in-system. In an FPGA-based dynamically reconfigurable system, a task scheduling algorithm which takes into account a reconfiguration time is required to minimize the runtime of an application running on the system. In this paper, we propose a scheduling algorithm for the dynamic reconfigurable system based on multiple FPGAs. The objective of the algorithm is to minimize the system runtime of the application. A task execution time and a processing FPGA allocation are determined under given FPGA resources and execution order of tasks. In the algorithm, we define a criterion how much the task execution time and the reconfiguration time influence delays of the system runtime of the application and we balance task delays based on the criterion by gradually reducing scheduling candinates of each task. Therefor, we can keep the delays of the system runtime of the application down by taking account of the number of reconfigurations. Experimental results demonstrate the efficiency and effectiveness of the algorithm. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / scheduling / reconfigurable system / dynamic reconfiguration / digital signal processing |
| Paper # | VLD2000-115,CPSY2000-70 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2001/1/4(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Scheduling Algorithm for a Dynamic Reconfigurable System Based on Multiple FPGAs |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | scheduling |
| Keyword(3) | reconfigurable system |
| Keyword(4) | dynamic reconfiguration |
| Keyword(5) | digital signal processing |
| 1st Author's Name | Takashi ISHITOBI |
| 1st Author's Affiliation | Dept. of Electronics, Information and Communication Engineering, Waseda University() |
| 2nd Author's Name | Nozomu TOGAWA |
| 2nd Author's Affiliation | Advanced Reserch Center for Science and Engineering, Waseda University |
| 3rd Author's Name | Masao YANAGISAWA |
| 3rd Author's Affiliation | Dept. of Electronics, Information and Communication Engineering, Waseda University |
| 4th Author's Name | Tatsuo OHTSUKI |
| 4th Author's Affiliation | Dept. of Electronics, Information and Communication Engineering, Waseda University |
| Date | 2001/1/4 |
| Paper # | VLD2000-115,CPSY2000-70 |
| Volume (vol) | vol.100 |
| Number (no) | 531 |
| Page | pp.pp.- |
| #Pages | 8 |
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