Presentation 2000/11/23
Analyzing Path Delay Fault Testability of RTL Data Paths:A Non-Scan Approach
Md. Altaf-UI-Amin, Satoshi Ohtake, Hideo Fujiwara,
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Abstract(in English) In this paper we analyze the testability of RTL data paths targeting all detectable path delay faults. The concept of RTL path is introduced. Based on this concept a definition for2-pattern(path delay fault)testable data path is developed. Some necessary and sufficient conditions to support the propagation of 2-pattern vectors for two or more control paths are pointed out. A graph approach of our analysis is also presented.
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Keyword(in English) Path delay faults / RTL data paths / Testability / 2-pattern test / control/observation paths
Paper # VLD2000-106,ICD2000-163,FTS2000-71
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Committee VLD
Conference Date 2000/11/23(1days)
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Registration To VLSI Design Technologies (VLD)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Analyzing Path Delay Fault Testability of RTL Data Paths:A Non-Scan Approach
Sub Title (in English)
Keyword(1) Path delay faults
Keyword(2) RTL data paths
Keyword(3) Testability
Keyword(4) 2-pattern test
Keyword(5) control/observation paths
1st Author's Name Md. Altaf-UI-Amin
1st Author's Affiliation Graduate School of Information Science Nara Institute of Science and Technology()
2nd Author's Name Satoshi Ohtake
2nd Author's Affiliation Graduate School of Information Science Nara Institute of Science and Technology
3rd Author's Name Hideo Fujiwara
3rd Author's Affiliation Graduate School of Information Science Nara Institute of Science and Technology
Date 2000/11/23
Paper # VLD2000-106,ICD2000-163,FTS2000-71
Volume (vol) vol.100
Number (no) 473
Page pp.pp.-
#Pages 6
Date of Issue