| Presentation | 2000/11/23 Realization of Multiple-output LUT Networks using TDM Tsutomu SASAO, Munehiro MATSUURA, Yukihiro IGUCHI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A realization of multiple-output logic function using a large look-up table(LUT)and a sequencer is presented. First, a multiple-output function is represented by an encoded characteristic function for non-zeros(ECFN). Then, it is represented by a cascade of look-up tables(LUTs). And finally, the cascade is simulated by a large LUT and a sequencer. We represent multiple-output functions for benchmark functions by cascades of LUTs, and show the number of LUTs and levels of networks. This realization is used for hardware logic simulator. A partition method of outputs for parallel evaluation is also presented. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Hardware for logic simulation / Multiple-output logic function / Functional decomposition / Cascade realization / FPGA synthesis / Time domain multiplexing(TDM) |
| Paper # | VLD2000-97,ICD2000-154,FTS2000-62 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2000/11/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Realization of Multiple-output LUT Networks using TDM |
| Sub Title (in English) | |
| Keyword(1) | Hardware for logic simulation |
| Keyword(2) | Multiple-output logic function |
| Keyword(3) | Functional decomposition |
| Keyword(4) | Cascade realization |
| Keyword(5) | FPGA synthesis |
| Keyword(6) | Time domain multiplexing(TDM) |
| 1st Author's Name | Tsutomu SASAO |
| 1st Author's Affiliation | Department of Computer Science and Electronics, Kyushu Institute of Technology:Center for Microelectronic Systems, Kyushu Institute of Technology() |
| 2nd Author's Name | Munehiro MATSUURA |
| 2nd Author's Affiliation | Department of Computer Science and Electronics, Kyushu Institute of Technology |
| 3rd Author's Name | Yukihiro IGUCHI |
| 3rd Author's Affiliation | Department of Computer Science, Meiji University |
| Date | 2000/11/23 |
| Paper # | VLD2000-97,ICD2000-154,FTS2000-62 |
| Volume (vol) | vol.100 |
| Number (no) | 473 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |