| Presentation | 2000/11/23 Area/Delay Estimation Techiques for Processors with Content Addressable Memory Tatsuhiko YODEN, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A hardware/software cosynthesis which synthesizes processors with a CAM(Content Addressable Memory)unit requires area/delay estimation of a generated processor. We, at first, configure processors with CAM unit based on several parameters, the results are logic-synthesized, and the figures of logic circuit are analyzed to obtain rough estimation equations of area and delay. Based on the obtained estimation equations of area and delay, we configure variety of processors of various types of parameter, the results are logic-synthesized, and the final estimation equations are established. We have compared the established estimation equations with the logic-synthesized processor's area and delay. Errors of the area estimations are less than 2.7%. Errors of the delay astimations are less than 3.8%. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | processor / CAM / area/delay estimation / hardware/software codesign |
| Paper # | VLD2000-83,ICD2000-140,FTS2000-48 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2000/11/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Area/Delay Estimation Techiques for Processors with Content Addressable Memory |
| Sub Title (in English) | |
| Keyword(1) | processor |
| Keyword(2) | CAM |
| Keyword(3) | area/delay estimation |
| Keyword(4) | hardware/software codesign |
| 1st Author's Name | Tatsuhiko YODEN |
| 1st Author's Affiliation | Dept.of Electronics, Information and Communication Engineering, Waseda University() |
| 2nd Author's Name | Nozomu TOGAWA |
| 2nd Author's Affiliation | Advanced Reserch Center for Science and Engineering, Waseda University |
| 3rd Author's Name | Masao YANAGISAWA |
| 3rd Author's Affiliation | Dept.of Electronics, Information and Communication Engineering, Waseda University |
| 4th Author's Name | Tatsuo OHTSUKI |
| 4th Author's Affiliation | Dept.of Electronics, Information and Communication Engineering, Waseda University |
| Date | 2000/11/23 |
| Paper # | VLD2000-83,ICD2000-140,FTS2000-48 |
| Volume (vol) | vol.100 |
| Number (no) | 473 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |