| Presentation | 2000/11/23 LUT Granularity Evaluation for Reconfigurable Logic nasahiro Iida, Toshinori Sueyoshi, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | There are some problems in present FPGA that a reconfiguration takes time. These are the cause that performance with the reconfigurable computing can't be drawn. In this paper, We cleared the necessary condition of the programable logic which is suitable for the reconfigurable computing and evaluated about the granularity of LUT on three measures of the implementation area, the critical path delay and the implementation efficiency. As a result, it was found out that the LUT granularity that it got a minimum area became large when fixed field in the logic block increase. Moreover, as for the critical path delay, the best LUT granularity varied in the circuit, and 5-LUT showed minimum delay on the average of the evaluation circuit. Then, implementation efficiency was decrease in according to LUT granularity's becoming large, and it was found out that it was less than 50% in 7-LUT. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | reconfigurable logic / FPGA / LUT / granularity |
| Paper # | VLD2000-82,ICD2000-139,FTS2000-47 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2000/11/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | LUT Granularity Evaluation for Reconfigurable Logic |
| Sub Title (in English) | |
| Keyword(1) | reconfigurable logic |
| Keyword(2) | FPGA |
| Keyword(3) | LUT |
| Keyword(4) | granularity |
| 1st Author's Name | nasahiro Iida |
| 1st Author's Affiliation | Graduate School of Science and Technology, Kumamoto University() |
| 2nd Author's Name | Toshinori Sueyoshi |
| 2nd Author's Affiliation | Department of Computer Science, Faculty of Engineering, Kumamoto University |
| Date | 2000/11/23 |
| Paper # | VLD2000-82,ICD2000-139,FTS2000-47 |
| Volume (vol) | vol.100 |
| Number (no) | 473 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |