| Presentation | 2000/11/23 A Statistical Delay-Uncertainty Analysis of Path-Balanced Circuits Masanori Hashimoto, Hidetoshi Onodera, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper discusses the statistical effect of performance optimization to the uncertainty in circuit delay. Performance optimization has an effect of balancing the delay of each path in the circuit, i, e. the delay of long paths are shortened and the delay of short paths are lengthened. In these path-balanced circuits, the uncertainty in circuit delay, which are caused by calculation error, manufacturing variability, fluctuation of operating condition, etc., becomes worse by the statistical characteristic of delay. Thus, a highly-optimized circuit may not satisfy delay constraints. In this paper, we demonstrate some examples that statistically-distributed circuit delay is increased by path-balancing, and we then raise a problem that performance optimization increases the uncertainty in circuit delay. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Delay Uncertainty / Statistical Delay Analysis / Performance Optimization / Path--Balance / Delay Fluctuation |
| Paper # | VLD2000-72,ICD2000-129,FTS2000-37 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2000/11/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Statistical Delay-Uncertainty Analysis of Path-Balanced Circuits |
| Sub Title (in English) | |
| Keyword(1) | Delay Uncertainty |
| Keyword(2) | Statistical Delay Analysis |
| Keyword(3) | Performance Optimization |
| Keyword(4) | Path--Balance |
| Keyword(5) | Delay Fluctuation |
| 1st Author's Name | Masanori Hashimoto |
| 1st Author's Affiliation | Department of Communications and Computer Engineering, Kyoto University() |
| 2nd Author's Name | Hidetoshi Onodera |
| 2nd Author's Affiliation | Department of Communications and Computer Engineering, Kyoto University |
| Date | 2000/11/23 |
| Paper # | VLD2000-72,ICD2000-129,FTS2000-37 |
| Volume (vol) | vol.100 |
| Number (no) | 473 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |