| Presentation | 2000/11/23 A Statistical Static Timing Analyzer for CMOS Combinatorial Circuits Considering Correlations Between Delays Shuji Nishimoto, Shuji Tsukiyama, Masakaz Tanaka, Masahiro Fukui, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The VLSI physical design in deep sub-micron era requires a technique for estimating effects caused by manufacturing fluctuations on circuit performance, especially the critical path delay, so as to produce circuits satisfying required performances with high yield. If designers can estimate the distribution of critical path delays caused by manufacturing fluctuations, they can eliminate excessive margins so that they can design low power and high density circuits. In this paper, we present a new algorithm to estimate the distribution of the critical path delay of CMOS combinatorial circuits, with the use of the normal distribution as the model of delay fluctuations. The algorithm can treat not only correlations between distributions of path-delays but also correlations between distributions of transistor delays in a logic gate and between interconnect delays. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | static timing analysis / statistical approach / correlations / CMOS combinatorial circuits |
| Paper # | VLD2000-71,ICD2000-128,FTS2000-36 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2000/11/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Statistical Static Timing Analyzer for CMOS Combinatorial Circuits Considering Correlations Between Delays |
| Sub Title (in English) | |
| Keyword(1) | static timing analysis |
| Keyword(2) | statistical approach |
| Keyword(3) | correlations |
| Keyword(4) | CMOS combinatorial circuits |
| 1st Author's Name | Shuji Nishimoto |
| 1st Author's Affiliation | Department of Electrical, Electronic, and Communication Engineering, Chuo University() |
| 2nd Author's Name | Shuji Tsukiyama |
| 2nd Author's Affiliation | Department of Electrical, Electronic, and Communication Engineering, Chuo University |
| 3rd Author's Name | Masakaz Tanaka |
| 3rd Author's Affiliation | Advanced LSI Tecnology Development Center Corporate Semiconductor Development Division Matsushita Electric Industrial Co., Ltd. |
| 4th Author's Name | Masahiro Fukui |
| 4th Author's Affiliation | Advanced LSI Tecnology Development Center Corporate Semiconductor Development Division Matsushita Electric Industrial Co., Ltd. |
| Date | 2000/11/23 |
| Paper # | VLD2000-71,ICD2000-128,FTS2000-36 |
| Volume (vol) | vol.100 |
| Number (no) | 473 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |