Presentation 2000/9/15
Challenges on Modeling & Simulation for Sub-100nm Technology Node
Norihiko KOTANI,
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Abstract(in English) The miniaturization of device structure for LSIs that are the key components of information technology(IT)is going to be accelerated. As the technology node of 100nm becomes realistic, it is considered that the development of huge integrated LSIs becomes impossible without the simultaneous optimization of design and process. Therefore the technology and the design system for taking the process information prior to the process fixture and using them to design are needed. Process information is needed at the early stage of design, so that simulation is desired to take the information as early as possible. Since simulation is based on theories and algorithme, we have to consider both modeling and simulator. Many challenges should be tried not only about new physical and chemical models, numerical calculation, and software platform to verify the results of research and development but also about creating circumstances for research and development.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) simulation / modeling / process simulator / device simulator / circuit simulator / equipment simulator / compact model
Paper # VLD2000-62,SDM2000-135
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Conference Information
Committee VLD
Conference Date 2000/9/15(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Challenges on Modeling & Simulation for Sub-100nm Technology Node
Sub Title (in English)
Keyword(1) simulation
Keyword(2) modeling
Keyword(3) process simulator
Keyword(4) device simulator
Keyword(5) circuit simulator
Keyword(6) equipment simulator
Keyword(7) compact model
1st Author's Name Norihiko KOTANI
1st Author's Affiliation ULSI Development Center, Mitsubishi Electric Co.()
Date 2000/9/15
Paper # VLD2000-62,SDM2000-135
Volume (vol) vol.100
Number (no) 294
Page pp.pp.-
#Pages 6
Date of Issue