Presentation 2000/5/5
A High-Level Synthesis System for Reconfigurable Machine:RM-V
Tomokazu Muroya, Koji Hashimoto, Hirotada Takabayashi, Nobutaka Kuroki, Masahiro Numa,
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Abstract(in English) This paper presents a high-level synthesis system, called RMAC-V(Reconfigurable Machine Application Compiler for RM-V), for applications using SDRAMs implemented on the flexible architecture of RM-V(Reconfigurable Machine-V)combining FPGAs and memories. Given an application program written in the C language, RMAC-V produces an RT-level hardware description in VHDL. To reduce the clock counts needed to access memories, RMAC-V introduces two techniques:multi-clock scheduling and preloading row address. Experimental results on Wavelet Transform Engine(WTE)have shown 33 % fewer total clock counts than those with conventional method.
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Keyword(in English) High-level synthesis / C language / Reconfigurable Machine / VHDL / FPGA / SDRAM
Paper # VLD2000-7
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Committee VLD
Conference Date 2000/5/5(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A High-Level Synthesis System for Reconfigurable Machine:RM-V
Sub Title (in English)
Keyword(1) High-level synthesis
Keyword(2) C language
Keyword(3) Reconfigurable Machine
Keyword(4) VHDL
Keyword(5) FPGA
Keyword(6) SDRAM
1st Author's Name Tomokazu Muroya
1st Author's Affiliation Kobe University()
2nd Author's Name Koji Hashimoto
2nd Author's Affiliation Mitsubishi Electric Corporation
3rd Author's Name Hirotada Takabayashi
3rd Author's Affiliation PFU Limited
4th Author's Name Nobutaka Kuroki
4th Author's Affiliation Kobe University
5th Author's Name Masahiro Numa
5th Author's Affiliation Kobe University
Date 2000/5/5
Paper # VLD2000-7
Volume (vol) vol.100
Number (no) 36
Page pp.pp.-
#Pages 7
Date of Issue