Presentation 2000/5/5
Automatic Generation of an Instruction-Set Level Simulator with the ASIP Development System PEAS-III
Tomohide Maeda, Yoshinori Takeuchi, Masaharu Imai, Akira Kitajima,
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Abstract(in English) An automatic generation method of an instruction-set level simulator with the ASIP development system PEAS-III is proposed. In this method, the pipeline processor model which is used in PEAS-III is represented in a software language and the program derived from the model can be execute as a simulator for a given processor description. Since SystemC is the language for simulators in our method, modeling of pipeline stages as concurrent processes is easy. In addition, with the cycle-based simulation kernel enables accurate and shorter-time simulation for pipeline processors. Experimental results show that simulation time of our simulator for a processor generated with PEAS-III is around 7 times than a VHDL simulator's.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) ASIP / Simulator Generation / SystemC / PEAS-III
Paper # VLD2000-5
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Committee VLD
Conference Date 2000/5/5(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Automatic Generation of an Instruction-Set Level Simulator with the ASIP Development System PEAS-III
Sub Title (in English)
Keyword(1) ASIP
Keyword(2) Simulator Generation
Keyword(3) SystemC
Keyword(4) PEAS-III
1st Author's Name Tomohide Maeda
1st Author's Affiliation Department of Informatics and Mathematical Science Graduate School of Engineering Science, Osaka University()
2nd Author's Name Yoshinori Takeuchi
2nd Author's Affiliation Department of Informatics and Mathematical Science Graduate School of Engineering Science, Osaka University
3rd Author's Name Masaharu Imai
3rd Author's Affiliation Department of Informatics and Mathematical Science Graduate School of Engineering Science, Osaka University
4th Author's Name Akira Kitajima
4th Author's Affiliation Department of Informatics and Mathematical Science Graduate School of Engineering Science, Osaka University
Date 2000/5/5
Paper # VLD2000-5
Volume (vol) vol.100
Number (no) 36
Page pp.pp.-
#Pages 8
Date of Issue