Presentation	2000/3/3 Substrate-Biased Domino CMOS Circuit Design I: Circuit Simulation by BSIM3v3 Model Yoshinibu Sakai, Toshiro Akino,
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Abstract(in English)	By using new substrate-bias power lines [V_ '(>V_ ), V_'()]in addistion to common power supply lines [V_ ,V_],CMOS circuits could be modeled to have four kinds of threshold voltages by the four separated substrate-biases. We proposed a circuit scheme making the most of pull-up / pull-down MOSFETs with high V_T, which are biased by [V_ ', V_'].The source terminals of these transistors were only connected to the base of [V_ , V_][1].In this paper, we optimize the domono CMOS circuits based on 0.35μm design-rule by doing T-SPICE simulation with BSIM3v3 model. It is shown that the 4-parallel 3-input NAND combinational logic circuit with the driver inverter can reduce the delay time to 67%, and the area to 69%compared to the equivalent static CMOS logic circuit.
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Keyword(in English)	substrate-bias / threshold voltage / domino CMOS circuit / BSIM3v3 model
Paper #	VLD99-126,ICD99-283
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Committee	VLD
Conference Date	2000/3/3(1days)
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Paper Information
Registration To	VLSI Design Technologies (VLD)
Language	JPN
Title (in Japanese)	(See Japanese page)
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Title (in English)	Substrate-Biased Domino CMOS Circuit Design I: Circuit Simulation by BSIM3v3 Model
Sub Title (in English)
Keyword(1)	substrate-bias
Keyword(2)	threshold voltage
Keyword(3)	domino CMOS circuit
Keyword(4)	BSIM3v3 model
1st Author's Name	Yoshinibu Sakai
1st Author's Affiliation	Department of Electronic System and Information Engineering School of Biology-Oriented Science and Technology, Kinki University()
2nd Author's Name	Toshiro Akino
2nd Author's Affiliation	Department of Electronic System and Information Engineering School of Biology-Oriented Science and Technology, Kinki University
Date	2000/3/3
Paper #	VLD99-126,ICD99-283
Volume (vol)	vol.99
Number (no)	659
Page	pp.pp.-
#Pages	8
Date of Issue