Presentation 2000/3/3
A fast algorithm to compute the minimum clock period of Semi-Synchronous Circuits
Ryosuke Oishi, Atsushi Takahashi,
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Abstract(in English) The clock period of a synchronous circuit can become shorter if the clock input timing is properly scheduled, such a circuit is called a semi-synchronous circuit. The speed-up of the computation of the minimum clock period of a semi-synchronous circuit is important, since the computation is done iteratively in the design of it. In this paper, we propose a fast algorithm to compute the minimum clock period of a semi-synchronous circuit for given signal propagation delays between registers.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Semi-Synchronous Circuit / Clock Period / Delay / Minimum Cycle Mean
Paper # VLD99-125,ICD99-282
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Committee VLD
Conference Date 2000/3/3(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A fast algorithm to compute the minimum clock period of Semi-Synchronous Circuits
Sub Title (in English)
Keyword(1) Semi-Synchronous Circuit
Keyword(2) Clock Period
Keyword(3) Delay
Keyword(4) Minimum Cycle Mean
1st Author's Name Ryosuke Oishi
1st Author's Affiliation Acupuncture Informatics Research Center, GOTO College.()
2nd Author's Name Atsushi Takahashi
2nd Author's Affiliation Dept.of Electrical and Electronic Engrg., Tokyo Inst. of Tech.
Date 2000/3/3
Paper # VLD99-125,ICD99-282
Volume (vol) vol.99
Number (no) 659
Page pp.pp.-
#Pages 6
Date of Issue