| Presentation | 2000/3/3 Graph Planarization for Floorplanning with considering Global Routing Hongdeuk Kim, Mineo Kaneko, Satoshi Tayu, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Since the impact of wiring to the final VLSI system performances becomes larger, it is required to respect wiring lengths from the begining of the floorplaning. In this paper, a graph planarization method with considering global routing is proposed. The problem is formulated as to planarize a given circuit graph so that the sum of path lengths, each path of which corresponds to a connection requirement between two modules, is to minimized. The planarization is achieved incrementally with respect to graph edges. If a resultant graph is not planar, the lastly added edge is removed, and the shortest path is formed instead of this edge with allowing auxiliary edges if necessary. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Floorplanning / Graph Planarization / Quasi-dual graph / VLSI |
| Paper # | VLD99-121,ICD99-278 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2000/3/3(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Graph Planarization for Floorplanning with considering Global Routing |
| Sub Title (in English) | |
| Keyword(1) | Floorplanning |
| Keyword(2) | Graph Planarization |
| Keyword(3) | Quasi-dual graph |
| Keyword(4) | VLSI |
| 1st Author's Name | Hongdeuk Kim |
| 1st Author's Affiliation | Japan Advanced Institute of Science and Technology() |
| 2nd Author's Name | Mineo Kaneko |
| 2nd Author's Affiliation | Japan Advanced Institute of Science and Technology |
| 3rd Author's Name | Satoshi Tayu |
| 3rd Author's Affiliation | Japan Advanced Institute of Science and Technology |
| Date | 2000/3/3 |
| Paper # | VLD99-121,ICD99-278 |
| Volume (vol) | vol.99 |
| Number (no) | 659 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |