Presentation 2000/1/11
Node Codings for Implicit Representation of Binary Decision Diagrams
Hitoshi Yamauchi, Hiromitsu Takahashi,
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Abstract(in English) Binary Decision Diagrams(BDD)is used on computer aided design of VLSI, because of that's goodness of memory spacing on computers for representing boolean functions. Recently, though, big size boolean functions such that are not able to be represented by BDD appear on VLSI design. We presented an implicit representation of BDDs(〓BDD)which is a new representation method by representing characteristics of BDD in meaning of graph implicitly, and its improvement representation method to manipulate faster. In this paper, some node codings are presented. Codings of nodes of BDDs represented implicitly, is effective to 〓BDD's size.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) BDD / zero-supressed BDD / implicit representation / boolean function / computer aided design
Paper # VLD99-92,CPSY99-101
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Committee VLD
Conference Date 2000/1/11(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Node Codings for Implicit Representation of Binary Decision Diagrams
Sub Title (in English)
Keyword(1) BDD
Keyword(2) zero-supressed BDD
Keyword(3) implicit representation
Keyword(4) boolean function
Keyword(5) computer aided design
1st Author's Name Hitoshi Yamauchi
1st Author's Affiliation Department of Communication Engineering, Faculty of Computer Science and System Engineering, Okayama Prefectural University()
2nd Author's Name Hiromitsu Takahashi
2nd Author's Affiliation Department of Communication Engineering, Faculty of Computer Science and System Engineering, Okayama Prefectural University
Date 2000/1/11
Paper # VLD99-92,CPSY99-101
Volume (vol) vol.99
Number (no) 529
Page pp.pp.-
#Pages 8
Date of Issue