| Presentation | 1999/8/27 Time Sharing Resources of Gate Arrays Based on Altera's PLDs and MAX+PLUS II Baiming Wang, Yoshito Ueno, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Based on the PLD's advantages such as user-configuration, modifiability, higher performance and lower cost per function..., a new concept of resources of gate arrays in PLDs by time-sharing is proposed. The usage of MAX+PLUSII is extracted. The brief up-to-date informations about Altera are introduced. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Time-sharing resources of gate arrays / PLDs / MAX+PLUSII |
| Paper # | VLD99-55 |
| Date of Issue |
| Conference Information | |
| Committee | VLD |
|---|---|
| Conference Date | 1999/8/27(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
|---|---|
| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Time Sharing Resources of Gate Arrays Based on Altera's PLDs and MAX+PLUS II |
| Sub Title (in English) | |
| Keyword(1) | Time-sharing resources of gate arrays |
| Keyword(2) | PLDs |
| Keyword(3) | MAX+PLUSII |
| 1st Author's Name | Baiming Wang |
| 1st Author's Affiliation | The EDA Technology Center, College of Information Engineering, ShenzhenUniversity, P.R.China() |
| 2nd Author's Name | Yoshito Ueno |
| 2nd Author's Affiliation | Department of Information System Science, Faculty of Engineering, Soka University |
| Date | 1999/8/27 |
| Paper # | VLD99-55 |
| Volume (vol) | vol.99 |
| Number (no) | 262 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |