Presentation 1999/6/11
A cell generation method for salicide process
Kazuhisa Okada, Takayuki Yamanouchi, Takasi Kambe,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) In this paper, we propose a cell generation method for salicide process, in which the diffusion areas of adjacent transistors are connected with salicide. Our method optimizes the transistor placement to improve cell area and delay considering the salicide connections which reduces metal wires and contacts. Because the salicide connections have higher degree of freedom than diffusion connection in conventional MOS process, the trade off between cell area and length should be consided in cell generartion for salicide process. In our method, we can regulate their priorities to set up evaluating function properly. The esperimental results shows that our method potimizes salicide connections efficiently, and generates some kinds of cells which have different features.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) salicide / cell generation / unit / standard cell
Paper # VLD99-43
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Conference Information
Committee VLD
Conference Date 1999/6/11(1days)
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Paper Information
Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A cell generation method for salicide process
Sub Title (in English)
Keyword(1) salicide
Keyword(2) cell generation
Keyword(3) unit
Keyword(4) standard cell
1st Author's Name Kazuhisa Okada
1st Author's Affiliation Design technology development center, Sharp corporation()
2nd Author's Name Takayuki Yamanouchi
2nd Author's Affiliation Design technology development center, Sharp corporation
3rd Author's Name Takasi Kambe
3rd Author's Affiliation Design technology development center, Sharp corporation
Date 1999/6/11
Paper # VLD99-43
Volume (vol) vol.99
Number (no) 108
Page pp.pp.-
#Pages 8
Date of Issue