| Presentation | 1999/6/11 Structure Method of High-Speed Redundant Binary Adder-Subtractor Representing Each Digit by Hybrid 2 Bits/3 Bits Masato Saito, Mitsuki Hinosugi, Yoshitaka Tsunekawa, Mamoru Miura, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Redundant binary representations diminish the latency of addition at moderate hardware cost and thus can play an important role in processor design. Usually it had been overlooked that the choice of good representation for digits is of crucial importance to high speed and efficient implementation. We propose a structure method of high-speed redundant binary adder-subtractor. This performs as fast as redundant binary adder, according to a new computation rule of subtraction and redundant binary number representing each digit by hybrid 2 bits/3 bits. By using the PARTHENON, a CAD system for VLSI, this adder-subtractor is designed and evaluated. As a result, the speed of proposed adder-subtractor is about 1.6 times as compared with the conventional redundant binary adder-subtractor. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | redundant binary representation / high-speed / subtractor / addre-subtractor / VLSI evaluation |
| Paper # | VLD99-41 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 1999/6/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Structure Method of High-Speed Redundant Binary Adder-Subtractor Representing Each Digit by Hybrid 2 Bits/3 Bits |
| Sub Title (in English) | |
| Keyword(1) | redundant binary representation |
| Keyword(2) | high-speed |
| Keyword(3) | subtractor |
| Keyword(4) | addre-subtractor |
| Keyword(5) | VLSI evaluation |
| 1st Author's Name | Masato Saito |
| 1st Author's Affiliation | Faculty of Engineering, Iwate University() |
| 2nd Author's Name | Mitsuki Hinosugi |
| 2nd Author's Affiliation | Faculty of Engineering, Iwate University |
| 3rd Author's Name | Yoshitaka Tsunekawa |
| 3rd Author's Affiliation | Faculty of Engineering, Iwate University |
| 4th Author's Name | Mamoru Miura |
| 4th Author's Affiliation | Faculty of Engineering, Iwate University |
| Date | 1999/6/11 |
| Paper # | VLD99-41 |
| Volume (vol) | vol.99 |
| Number (no) | 108 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |