Presentation | 1999/6/11 A Proposal of quasi-Parallel Divider for Numbers of Arbitary Word Length and its Application for VSI. Tsugio Nakamura, Hiroshi Kasahara, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | We propose a new modularization technique of a hardware for virtual socket interface (VSI), where a proposed quasi-parallel divider (multiplier) for numbers of arbitraty word length is embedded as a virtual component (VC). This component reduces the increase in the number of pins and gates, but not failing the high-speed performance characteristics of the parallel divider, by cascading some parallel dividers (multipliers) and repeating the arithmetic poerations using minimum clock cycles. By this bit length free arithmetic unit, each VC module becomes easily adaptable for many functions as if it is a data processing unit in an object of object-oriented engineering. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Parallel divider / Expandable function / Chip slice / VSI / Macro-cell |
Paper # | VLD99-40 |
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Conference Information | |
Committee | VLD |
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Conference Date | 1999/6/11(1days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | |
Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | VLSI Design Technologies (VLD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A Proposal of quasi-Parallel Divider for Numbers of Arbitary Word Length and its Application for VSI. |
Sub Title (in English) | |
Keyword(1) | Parallel divider |
Keyword(2) | Expandable function |
Keyword(3) | Chip slice |
Keyword(4) | VSI |
Keyword(5) | Macro-cell |
1st Author's Name | Tsugio Nakamura |
1st Author's Affiliation | Kokusai Junior College() |
2nd Author's Name | Hiroshi Kasahara |
2nd Author's Affiliation | Tokyo Denki University |
Date | 1999/6/11 |
Paper # | VLD99-40 |
Volume (vol) | vol.99 |
Number (no) | 108 |
Page | pp.pp.- |
#Pages | 8 |
Date of Issue |