Presentation	1999/6/11 A Capacitance Extraction Method for Deep-submicron LSI Design Susumu Kobayashi, Masato Edahiro,
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Abstract(in English)	Recently, the influence of wire delay on LSI performance has increased, which makes the capacitance extraction more important. Especially in deep-submicron LSI, a new capacitance extraction method which can deal with the increasing coupling capacitance between neighboring wires is needed. Also, the capacitance extraction method needs to be fast enough to handle very large scale circuits in deep-submicron process. We propose a new capacitance extraction method for deep-submicron process. The method takes advantage of regularity of the multi-level interconnect structure and divides a target wire adequately, which leads to fast and accurate extraction.
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Keyword(in English)	LSI CAD / capacitance extaction / deep-submicrion process / multi-level interconnect structure
Paper #	VLD99-37
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Conference Information
Committee	VLD
Conference Date	1999/6/11(1days)
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Paper Information
Registration To	VLSI Design Technologies (VLD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	A Capacitance Extraction Method for Deep-submicron LSI Design
Sub Title (in English)
Keyword(1)	LSI CAD
Keyword(2)	capacitance extaction
Keyword(3)	deep-submicrion process
Keyword(4)	multi-level interconnect structure
1st Author's Name	Susumu Kobayashi
1st Author's Affiliation	C&C Media Research Laboratories, NEC Corporation()
2nd Author's Name	Masato Edahiro
2nd Author's Affiliation	C&C Media Research Laboratories, NEC Corporation
Date	1999/6/11
Paper #	VLD99-37
Volume (vol)	vol.99
Number (no)	108
Page	pp.pp.-
#Pages	6
Date of Issue