Presentation	1999/6/11 Delay Minimization Using a Network Flow Algorithm Yutaka TAMIYA,
PDF Download Page	PDF download Page Link
Abstract(in Japanese)	(See Japanese page)
Abstract(in English)	We propose a new method to optimize delays of a very large circuit. We find time best set of local transforms to be applied to the circuit, by adding "padding nodes" on non-critical edges of the circuit, and calculating separator sets of the circuit using a network flow algorithrm. Our method is robust for very large circuits, because its memory usage and calculation time are linear and polynomial order with the size of the circuit. According to our experimental results, our method has accomplished all circuits, while K. J. Singh's selection function-based method has aborted with three large circuits because of memory overflow. The results also shows our method has a comparable capability in delay optimization to Singh's method.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	VLSI / logic synthesis / delay optimization / separator set / maximum flow algorithm
Paper #	VLD99-35
Date of Issue

Conference Information
Committee	VLD
Conference Date	1999/6/11(1days)
Place (in Japanese)	(See Japanese page)
Place (in English)
Topics (in Japanese)	(See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To	VLSI Design Technologies (VLD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Delay Minimization Using a Network Flow Algorithm
Sub Title (in English)
Keyword(1)	VLSI
Keyword(2)	logic synthesis
Keyword(3)	delay optimization
Keyword(4)	separator set
Keyword(5)	maximum flow algorithm
1st Author's Name	Yutaka TAMIYA
1st Author's Affiliation	FUJITSU LABORATORIES LTD.()
Date	1999/6/11
Paper #	VLD99-35
Volume (vol)	vol.99
Number (no)	108
Page	pp.pp.-
#Pages	8
Date of Issue